1. Field of the Invention
The present invention relates to semiconductor devices and more specifically to dynamic memory devices, such as dynamic random access memory devices (DRAMs).
2. Description of Related Art
At the end of the testflow for every DRAM is the Burn-In module stress test and the Final module test. The purpose of these tests is to screen out all stress induced cell failures due to packaging and Burn-In. These tests perform a critical screening and characterization for memory cells, such as DRAM cells, which aid in identifying the retention time related failures at the module level. Retention time is determined by leakage current which has the effect of discharging the cell's high voltage or "1's" level to a lower voltage that makes it fail the read "1" operation. Leakage current occurs normally in DRAM cells, as predicted by semiconductor physics, but at sufficiently low values that correspond to retention times of several seconds. Present day DRAMs are tested and guaranteed for retention times of typically 128 milliseconds. This much shorter retention time provides margin for leakage currents higher than normal, and may allow for retention times between the specification value and the normal time of several seconds. These cells are considered weak and are potential reliability problems. It is desirable to design test methods which can identify and monitor these cells for degradation after stress. The identification of these cells is accomplished by signal margin testing.
The purpose of signal margin testing is to identify cells on the chip which are weaker than all other cells on the chip. These weaker cells are usually the result of defects. Although a weaker cell may function normally under typical operating conditions after initial fabrication, it may degrade with time or stress, and later fail after module assembly or after burn-in stress testing, or in a customer application.
Current test methods, however, typically require several thorough and in-depth analyses in order to identify the exact failure mechanisms. As technology advances, the number of memory cells of a memory device increases, requiring more time to test the memory, to detect defective bits, and afterwards, to characterize their failure mechanisms. The defective modules are then analyzed during the Physical Failure Analysis (PFA) to identify the failure mechanisms and any root causes. The PFA, however, is a very thorough but time consuming process. A major productivity enhancement can be achieved by providing the PFA analyst more detailed data about the expected failure mechanisms and failure classifications.
Conventional methods to characterize retention related failures include operating a set of test patterns on the whole memory array, and varying the refresh cycle time. Any leakage current in the device will cause a decrease of charge in the memory cell, and hence, reduce the retention time. FIG. 1 depicts the cross-section of an n-polysilicon memory cell 10 with a p-well 12 and an NFET Array Device 14 and Wordline (WL) 16. The contact area of the memory cell's n-polysilicon 10 and the plate voltage area 18 form a cell capacitor. The p-well voltage is held at a negative potential and forms the back bias of the array device. It has an electrical connection via the p-well contact 26. Typically, two leakage currents can be established, junction leakage 20, I.sub.jct, and subthreshold leakage 22, I.sub.sub. The junction leakage is formed between the pn-junction of the p-well 12 and the n-diffusion 14 of the cell. The subthreshold leakage represents the current between the bitline 24 and the cell when the array is turned off, i.e., the wordline 16 potential is at zero volts. Any change in the back bias voltage (p-well voltage) will affect the two described leakage currents.
Thus, the ability to characterize retention related single bit failures remains a challenge in the art that has, to date, been performed by inefficiently varying the refresh cycle time of the device.
Special test conditions activated by a test code are taught in U.S. Pat. Nos. 5,469,393 and 5,544,108, issued to M. Thomann on Nov. 21, 1995 and Aug. 6, 1996, respectively. The first test condition connects the bit lines of the unselected half of a shared sense amp array to the bit lines of the selected half to produce twice the bit line capacitance and consequently half of the `read` signal level. A second method reduces the `read` margin by adjusting the cell capacitor plate voltage which can lower the logic level "1", or raise the logic level "0" node voltage in the cell with respect to the bit line read reference voltage level. A third method teaches higher bit line capacitance connected to an external capacitance via test mode switches or an external read reference voltage connected by the same switches. Such similar methods are taught by Taguchi in U.S. Pat. No. 5,339,273, issued on Aug. 16, 1994.
These signal margin test methods can identify cells which have weaker read output charge than other cells. Weaker read output charge can be the result of several possible defects or abnormalities within the cell, such as high junction leakage current, high sub-threshold current, parasitic leakage paths, low cell capacitance, and high connection resistance. It remains difficult under the prior art test methods to ascertain which defect caused the failure.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a test apparatus and methodology to characterize special single bit failures, cell retention time failures, due to leakage current, junction leakage current, or sub-threshold leakage current.
It is another object of the present invention to provide a test apparatus and methodology to perform a package level screen test that distinguishes between different failure mechanisms for packaged memory devices.
It is yet another object of the present invention to provide a test apparatus and methodology to shorten the test time for retention of related cell failures in the testing of memory devices.
Still other advantages of the invention will in part be obvious and will in part be apparent from the specification.